AWG G3 PAD FOR PS3 Dokumentacja Pobierz pdf (Strona 271)

X24C04

Characteristics subject to change without notice.

4 of 13

REV 1.1 7/12/00

www.xicor.com

NOT RECOMMENDED

FOR NEW DESIGNS

Figure 3. Acknowledge Response From Receiver

SCL From

Master

Data Output

From Transmitter

From Receiver

START

Acknowledge

Data Output

DEVICE ADDRESSING

Following a start condition the master must output the

address of the slave it is accessing. The most signiﬁ-

cant four bits of the slave are the device type identiﬁer

(see Figure 4). For the X24C04 this is ﬁxed as 1010[B].

Figure 4. Slave Addressing

The next two signiﬁcant bits address a particular

device. A system could have up to four X24C04

devices on the bus (see Figure 10). The four addresses

are deﬁned by the state of the A

and A

inputs.

The next bit of the slave address is an extension of the

array’s address and is concatenated with the eight bits

of address in the word address ﬁeld, providing direct

access to the whole 512 x 8 array.

Note:

This bit is part of word address. Not related to

device address pin A

The last bit of the slave address deﬁnes the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the X24C04 monitors the

SDA bus comparing the slave address being transmit-

ted with its slave address (device type and state of A

and A

inputs). Upon a correct compare the X24C04

outputs an acknowledge on the SDA line. Depending

on the state of the R/W bit, the X24C04 will execute a

read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24C04 requires a second

address ﬁeld. This address ﬁeld is the word address,

comprised of eight bits, providing access to any one of

the 512 words of memory. Upon receipt of the word

address the X24C04 responds with an acknowledge,

and awaits the next eight bits of data, again responding

with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time

the X24C04 begins the internal write cycle to the non-

volatile memory. While the internal write cycle is in

progress the X24C04 inputs are disabled, and the

device will not respond to any requests from the mas-

ter. Refer to Figure 5 for the address, acknowledge and

data transfer sequence.

R/W

Address

010A

Device Type

Identifier

Device

Word Address

High Order

1 2 ... 266 267 268 269 270 271 272 273 274 275 276 ... 284 285

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