AWG G3 PAD FOR PS3 Dokumentacja

System ReferenceSS1

Table of Contents10 System Reference, January 2001

4 Test Head Filling and DUT Board Considerations Test System Configuration100 System Reference, January 2001Table 19 Function of Utility Pogo Pads (10

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001101Figure 43 Position and Numbering of Utility

4 Test Head Filling and DUT Board Considerations Test System Configuration102 System Reference, January 2001Figure 44 Possible Positions for EEPROM on

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001103Table 21 Functional Assignment of EEPROM Pi

4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card104 System Reference, January 2001Wafer Prober DUT Board and Pro

Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001105DUT Board of Wafer ProberSee al

4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card106 System Reference, January 2001Figure 46 Schematic Drawing of

Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001107 Probe Card-Pogo Pad Assignment

4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card108 System Reference, January 2001DPS pogo pads The units next t

Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001109input-output pogo pads on thepr

List Of FiguresSystem Reference, January 200111List Of FiguresFigure 1 P- and C-Models of the Agilent93000 SOC Series 18Figure 2 The Agilent 93000 SOC

4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card110 System Reference, January 200117th signal lines on the probe

Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001111Table 23 Functional Assignment

4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card112 System Reference, January 2001Table 24 Functional Assignment

Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001113The abbreviations of the utili

4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card114 System Reference, January 2001Table 25 assigns the number of

System Reference, January 2001 11555 DUT Board Performance ConsiderationsThis chapter provides you with information on:• “Signal Traces” on page 116•

5 DUT Board Performance Considerations Signal Traces116 System Reference, January 2001Signal TracesLanding holes/vias are inside the landing pads. The

Signal Traces 5 DUT Board Performance ConsiderationsSystem Reference, January 2001117with higher pin count. Without these dummy pads, the pogo pins of

5 DUT Board Performance Considerations Maintaining Signal Fidelity118 System Reference, January 2001Maintaining Signal FidelityBecause the tester does

Maintaining Signal Fidelity 5 DUT Board Performance ConsiderationsSystem Reference, January 2001119Signal InhomogeneitiesInhomogeneities cause reflect

List Of Figures12 System Reference, January 2001Figure 34 Position of Analog and Digital Pad Blocks within Groups 69Figure 35 Group reservation of th

5 DUT Board Performance Considerations Correctly Terminating Signal Lines120 System Reference, January 2001Correctly Terminating Signal LinesThe guide

Correctly Terminating Signal Lines 5 DUT Board Performance ConsiderationsSystem Reference, January 2001121Terminating Output PinsOutput pins are not a

5 DUT Board Performance Considerations Correctly Terminating Signal Lines122 System Reference, January 2001Termination Checklist50 Ohm Environment If

Reducing I/O Round-Trip Times 5 DUT Board Performance ConsiderationsSystem Reference, January 2001123Reducing I/O Round-Trip TimesFor bidirectional pi

5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests124 System Reference, January 2001DUT Board Design for Mixed-Signal Test

DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance ConsiderationsSystem Reference, January 2001125• Problems will occur: Ensure that the

5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests126 System Reference, January 2001Grounding and Signal ShieldingGroundin

DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance ConsiderationsSystem Reference, January 2001127Matching the impedance of the signal so

5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests128 System Reference, January 2001• Bypass capacitors should include ele

DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance ConsiderationsSystem Reference, January 2001129Printed Circuit BoardTo run the same ap

List Of FiguresSystem Reference, January 200113Figure 60 Relation Between Load Capacitance and Voltage Ripple - Range 1m148Figure 61 Relation Between

5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests130 System Reference, January 2001where Er means the relative dielectric

DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance ConsiderationsSystem Reference, January 2001131Figure 53 Sharp CornerIn the above exam

5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests132 System Reference, January 2001Figure 55 Signal LinesTo avoid the cro

DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance ConsiderationsSystem Reference, January 2001133Consider the following measures:• Chang

5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests134 System Reference, January 2001

System Reference, January 2001 13566 Device PowerSupplyThis chapter provides you with information about the various Power Supplies available for the A

6 Device PowerSupply General Purpose Power Supply (GPDPS)136 System Reference, January 2001General Purpose Power Supply (GPDPS)This section provides y

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001137To best adapt DPS channels to the appropriate test requireme

6 Device PowerSupply General Purpose Power Supply (GPDPS)138 System Reference, January 2001Important features of the General Purpose Device Power Supp

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001139GPDPS Specifications.The following supply voltage/current ra

List Of Figures14 System Reference, January 2001Figure 96 Example for Using Loop Back Route 213Figure 97 Coherent Sampling 217Figure 98 Sampler Block

6 Device PowerSupply General Purpose Power Supply (GPDPS)140 System Reference, January 2001Figure 58 General Purpose Power Supply: Power DiagramNOTE C

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001141Setting up Performance RangesTo fully exploit the benefits o

6 Device PowerSupply General Purpose Power Supply (GPDPS)142 System Reference, January 2001An essential component of the GPDPS is the load capac-itor

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001143Why are Performance Ranges Useful?Performance Ranges guarant

6 Device PowerSupply General Purpose Power Supply (GPDPS)144 System Reference, January 20014. Find out the maximum voltage ripple your DUT can tolerat

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001145– Load C 4µF to < 20µF selects the performance range 2–Lo

6 Device PowerSupply General Purpose Power Supply (GPDPS)146 System Reference, January 2001• load capacitanceBasically, each performance range require

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001147The following table helps you to find the appropriate perfor

6 Device PowerSupply General Purpose Power Supply (GPDPS)148 System Reference, January 2001range of 100mA to 400mA, performance range 3 typically for

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001149Figure 61 Relation Between Load Capacitance and Voltage Ripp

System Reference, January 2001 1511 System OverviewThis chapter provides you with information on:• “System Characterization” on page 18• “Major Compon

6 Device PowerSupply General Purpose Power Supply (GPDPS)150 System Reference, January 2001Figure 63 Relation Between Load Capacitance and Voltage Rip

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001151If you further increase the load capacitance, the initial vo

6 Device PowerSupply General Purpose Power Supply (GPDPS)152 System Reference, January 2001Measurement in Performance Range 2Figure 66 Load regulation

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001153Measurement in Performance Range 4Figure 68 Load regulation

6 Device PowerSupply General Purpose Power Supply (GPDPS)154 System Reference, January 2001The effect of a high load capacitance in this performance r

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001155Table 29 Bypass Capacitance to Filter Out GPDPS Related Nois

6 Device PowerSupply General Purpose Power Supply (GPDPS)156 System Reference, January 2001If the trigger signal goes from 0V to 5V, Vbump is triggere

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001157Voltage Settling TimesThe voltage settling time is defined b

6 Device PowerSupply General Purpose Power Supply (GPDPS)158 System Reference, January 2001Figure 72 Voltage settling, load capacitance 100µFThis plot

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001159If the load capacitor is too high the DPS channel switches i

1 System Overview Revision History16 System Reference, January 2001Revision HistoryChanges from Revision 1.0 (Aug. 99) to Revision 1.1 (Oct. 99)The Ch

6 Device PowerSupply General Purpose Power Supply (GPDPS)160 System Reference, January 2001The channels of one ganged group have to be in sequence (e.

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001161All Power (Force+) and Ground (Force–) pins and all Sense pi

6 Device PowerSupply General Purpose Power Supply (GPDPS)162 System Reference, January 2001Disconnecting the DPSA connected DPS forces the programmed

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001163Routing DPS LinesEnsure that Power and Ground lines are laid

6 Device PowerSupply General Purpose Power Supply (GPDPS)164 System Reference, January 2001Current and Voltage Measurements with DPSDevice Operation S

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 20011654. Device stop: Wait time due to transient time of the volta

6 Device PowerSupply General Purpose Power Supply (GPDPS)166 System Reference, January 2001Table 30 Wait time required for measurement path to settle3

General Purpose Power Supply (GPDPS) 6 Device PowerSupplySystem Reference, January 2001167Sample IDDQ Current Settling TimeThe table below shows the s

6 Device PowerSupply High Current Power Supply (HCDPS)168 System Reference, January 2001High Current Power Supply (HCDPS)This section provides you wit

High Current Power Supply (HCDPS) 6 Device PowerSupplySystem Reference, January 2001169Connection to DUT BoardThe HCDPS is connected to the DUT Board

Revision History 1System OverviewSystem Reference, January 2001 17Changes from Revision 2.2(Jun. 00) to Revision 3.0 (Feb 01)The Chapter7 “Analog Modu

6 Device PowerSupply High Current Power Supply (HCDPS)170 System Reference, January 2001Block DiagramThe following figure shows, in principal, the lay

High Current Power Supply (HCDPS) 6 Device PowerSupplySystem Reference, January 20011712. The multiphase stepdown converterThis converter steps down t

6 Device PowerSupply High Current Power Supply (HCDPS)172 System Reference, January 2001c. Over-temperature ProtectionIt is possible to add a heat or

High Current Power Supply (HCDPS) 6 Device PowerSupplySystem Reference, January 2001173e. Over-current ProtectionThere are two modes to be considered

6 Device PowerSupply High Current Power Supply (HCDPS)174 System Reference, January 20015. Diagnostic CircuitsAs with the General Purpose and High Vol

High Current Power Supply (HCDPS) 6 Device PowerSupplySystem Reference, January 2001175diagnostics. This means, that you cannot run any other tests wh

6 Device PowerSupply High Current Power Supply (HCDPS)176 System Reference, January 2001HCDPS SpecificationsNote that in contrast to the General Purpo

High Current Power Supply (HCDPS) 6 Device PowerSupplySystem Reference, January 2001177HCDPS Switching Voltages (Vbump)This is described in “Switching

6 Device PowerSupply High Current Power Supply (HCDPS)178 System Reference, January 2001Current and Voltage MeasurementAs with the General Purpose and

High Current Power Supply (HCDPS) 6 Device PowerSupplySystem Reference, January 2001179disconnect is a hardware functionality which is only available

1 System Overview System Characterization18 System Reference, January 2001System CharacterizationThe Agilent 93000 SOC Series offers solutions for tes

6 Device PowerSupply High Current Power Supply (HCDPS)180 System Reference, January 2001Syntax:HSCM {mode}HSCM? {mode}returnsHSCM {mode}Parameters:mod

High Voltage Power Supply (HVDPS) 6 Device PowerSupplySystem Reference, January 2001181High Voltage Power Supply (HVDPS)This section provides you with

6 Device PowerSupply High Voltage Power Supply (HVDPS)182 System Reference, January 2001also the section “Setting up Performance Ranges” on page 141 f

System Reference, January 2001 18377 Analog ModulesTesting of mixed-signal devices requires analog resources for applying highly accurate analog signa

7 Analog Modules Waveform Generators184 System Reference, January 2001Waveform GeneratorsThere are three types of AWGs available as follows:• High Res

Waveform Generators 7 Analog ModulesSystem Reference, January 2001185Figure 79 Analog Waveform GenerationThe AWGs start waveform generation by enterin

7 Analog Modules Waveform Generators186 System Reference, January 2001The following tables show the key specifications of the AWGs.Specification Value

Waveform Generators 7 Analog ModulesSystem Reference, January 2001187Specification ValuePin counts per mod-ule8 single-ended (4 parallel test) or 4 di

7 Analog Modules Waveform Generators188 System Reference, January 2001Specification ValuePin counts per module8 single-ended (2 parallel test) or 4 di

Waveform Generators 7 Analog ModulesSystem Reference, January 2001189Theory of Operation for High Resolution and High Speed AWGsThis section describes

System Characterization 1 System OverviewSystem Reference, January 200119MACH-D Testing Systems-on-a-Chip (SOC devices) means having the capability an

7 Analog Modules Waveform Generators190 System Reference, January 2001Output MultiplexerThe output multiplexer can make the following connec-tions:• O

Waveform Generators 7 Analog ModulesSystem Reference, January 2001191Figure82 Output Routes (Differential)A single-ended signal or a pair of different

7 Analog Modules Waveform Generators192 System Reference, January 2001DC RoutesThe output multiplexer can make the route between a pogo pin and the SY

Waveform Generators 7 Analog ModulesSystem Reference, January 2001193Figure84 Loop Back RoutesThe loop back route is designed so that the line impedan

7 Analog Modules Waveform Generators194 System Reference, January 2001AttenuatorThe attenuator adjusts the amplitude of the signal gener-ated by the d

Waveform Generators 7 Analog ModulesSystem Reference, January 2001195Sequencer and Waveform MemoryThe sequencer controls the output sequence of the wa

7 Analog Modules Waveform Generators196 System Reference, January 2001Theory of Operation for Ultra High Speed AWGThis section describes the theory of

Waveform Generators 7 Analog ModulesSystem Reference, January 2001197one AWG instrument shown as the upper block in the above figure. For one AWG inst

7 Analog Modules Waveform Generators198 System Reference, January 2001To output a pair of differential signals, A+ and A-, or B+ and B- can be used fo

Waveform Generators 7 Analog ModulesSystem Reference, January 2001199DC RoutesThe front-end module can make the route between a pogo pin (including th

2 System Reference, January 2001System ReferenceAgilent 93000 SOC P–Series and C–SeriesAgilent Technologies GmbHSOC Business UnitAgilent Part No. E705

1 System Overview System Characterization20 System Reference, January 2001Technical HighlightsTest Processor-Per-PinArchitectureThe technology require

7 Analog Modules Waveform Generators200 System Reference, January 2001Loop Back RoutesThe front-end module can make the loop back route between A+ and

Waveform Generators 7 Analog ModulesSystem Reference, January 2001201AWG InstrumentThe AWG instrument is installed in the analog support rack. The AWG

7 Analog Modules Waveform Generators202 System Reference, January 2001Clock OscillatorThe clock oscillator generates the conversion clock and provides

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001203Waveform DigitizersThere are two types of waveform digitizers available as follow

7 Analog Modules Waveform Digitizers204 System Reference, January 2001When the digitizer starts, no initial discard points are stored. The digitizer s

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001205To achieve coherent sampling, the measured signals should be periodic and you nee

7 Analog Modules Waveform Digitizers206 System Reference, January 2001The following tables show the key specifications of the waveform digitizers.Spec

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001207Specification ValuePin counts per module8 single-ended or 4 differentialResolutio

7 Analog Modules Waveform Digitizers208 System Reference, January 2001Theory of OperationThis section describes the theory of operation for digi-tizer

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001209Input MultiplexerThe input multiplexer can make the following connec-tions:•Input

System Characterization 1 System OverviewSystem Reference, January 200121Figure 4 SOC System IntegrationIn order to achieve this high level of integra

7 Analog Modules Waveform Digitizers210 System Reference, January 2001Figure 93 Input Resistanceinputres2High Resolution Digitizer 1 Mohm

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001211DC RoutesThe input multiplexer can make the route between a pogo pin and the SYNC

7 Analog Modules Waveform Digitizers212 System Reference, January 2001Loop Back RoutesThe input multiplexer can make the loop back route between any p

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001213lution digitizer for another test item for the Aout pin. When K1 and K3 are close

7 Analog Modules Waveform Digitizers214 System Reference, January 2001Input AmplifierThe input amplifier determines the input voltage range. Any input

Waveform Digitizers 7 Analog ModulesSystem Reference, January 2001215Sequencer and Waveform MemoryThe sequencer controls storage of digitized data int

7 Analog Modules Sampler216 System Reference, January 2001SamplerThere is one type of sampler available as follows:• Dual High Speed Sampler (1 GHz 12

Sampler 7 Analog ModulesSystem Reference, January 2001217In the sampler, the sampling period (T) is slightly different (∆t) from a multiple of the sig

7 Analog Modules Sampler218 System Reference, January 2001You can observe or analyze the captured waveform data with the software interface, Mixed-Sig

Sampler 7 Analog ModulesSystem Reference, January 2001219Theory of OperationThis section describes the theory of operation for a sampler. The followin

1 System Overview System Characterization22 System Reference, January 2001• Maximum of 8 DPS boards (960 pins testhead) containing 4 DPS channels each

7 Analog Modules Sampler220 System Reference, January 2001waveform memory are shared between two channels. The SYNC CLK and SYNC DATA pins are also sh

Sampler 7 Analog ModulesSystem Reference, January 2001221DC RoutesThe input multiplexer can make the route between a pogo pin and the SYNC CLK pin. Th

7 Analog Modules Sampler222 System Reference, January 2001Loop Back RoutesThe input multiplexer can make the loop back route between adjacent pogo pin

Sampler 7 Analog ModulesSystem Reference, January 2001223Sampler UnitThe sampler unit periodically samples the high speed input signal and holds it un

7 Analog Modules Sampler224 System Reference, January 2001The timing generator contains the delay counter and delay vernier. By using them, the timing

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001225Time Interval AnalyzerThere is one type of TIA available as follows: • High pe

7 Analog Modules Time Interval Analyzer226 System Reference, January 2001Figure 101 TIA Measurement FunctionsThe TIA can measure intervals with the sp

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001227• Period/Frequency MeasurementThis mode is used to measure the period or frequ

7 Analog Modules Time Interval Analyzer228 System Reference, January 2001• Pulse Width MeasurementThis mode is used to measure the negative or positiv

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001229• Propagation Delay MeasurementThis mode is used to measure the time differenc

Major Components 1 System OverviewSystem Reference, January 200123Major ComponentsThe Agilent 93000 SOC Series test system consists of• Testhead with

7 Analog Modules Time Interval Analyzer230 System Reference, January 2001• Auto Trigger modeThis mode uses the edge of the input signal to channel 1 o

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001231detection on channel 1, the edges on channel 2 are ignored. Thus, the measurem

7 Analog Modules Time Interval Analyzer232 System Reference, January 2001For a periodic signal, the jitter test has to measure multiple periods that a

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001233The following example shows the relationship of TrigDe-layCntStart, TrigDelayC

7 Analog Modules Time Interval Analyzer234 System Reference, January 2001Max. input frequency 960 MHz (Signal input 50 ohm)(Characteristics)Input volt

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001235The following tables show the key specifications of the General Purpose TIA. S

7 Analog Modules Time Interval Analyzer236 System Reference, January 2001Theory of OperationThis section describes the theory of operation for the TIA

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001237The front-end module has seven signal input pins and two trigger input pins. T

7 Analog Modules Time Interval Analyzer238 System Reference, January 2001The front-end module consists of the following three kinds of blocks: • Input

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001239• Determines the input impedance. You can select 10 kohm or 50 ohm as the inpu

1 System Overview Major Components24 System Reference, January 2001Figure 6 SOC Series Model with 448 Pins TestheadThe TestheadThe testhead is the hea

7 Analog Modules Time Interval Analyzer240 System Reference, January 2001• Routes one or two input pins among seven input pins to the TIA instrument.

Time Interval Analyzer 7 Analog ModulesSystem Reference, January 2001241Figure111 TIA Instrument Block DiagramThe TIA instrument has two signal inputs

7 Analog Modules Synchronization242 System Reference, January 2001SynchronizationThis section provides the following information for synchronizing bet

Synchronization 7 Analog ModulesSystem Reference, January 2001243Table 44 Trigger-to-Signal Delay, Accuracy, and UncertaintyWhere, “1 master clock per

7 Analog Modules Synchronization244 System Reference, January 2001Figure 112 Start Timing of Analog Module after Receiving TriggerIf a test requires h

Synchronization 7 Analog ModulesSystem Reference, January 2001245Trigger Line Length and SignalLine LengthIn addition, there are two kinds of signal d

7 Analog Modules Synchronization246 System Reference, January 2001Figure 114 Timing Chart and Delay FactorThe above timing chart is an example of anal

Synchronization 7 Analog ModulesSystem Reference, January 2001247to consider only trigger-to-signal delay. For the second level, your application need

7 Analog Modules Synchronization248 System Reference, January 2001Synchronization TriggerThe analog module has two pins dedicated for trigger input. O

Synchronization 7 Analog ModulesSystem Reference, January 2001249Adjusting Synchronization TimingConsidering Trigger-to-Signal Delay OnlyIf the trigge

Major Components 1 System OverviewSystem Reference, January 200125Figure 7 Agilent 93000 SOC Series TestheadFor detailed information on the tester ele

7 Analog Modules Synchronization250 System Reference, January 2001Considering Trigger-to-Signal Delay, Trigger Line, and Signal LineIf you cannot igno

Synchronization 7 Analog ModulesSystem Reference, January 2001251Adjusting Timing at Pogo Pin of Analog Module The following is the timing chart for m

7 Analog Modules Synchronization252 System Reference, January 2001Adjusting Timing at DUT PinAssuming the DUT pin as the reference point of timing, yo

Synchronization 7 Analog ModulesSystem Reference, January 2001253For a digitizer or sampler, you have to move the trigger signal edge backward by the

7 Analog Modules Synchronization254 System Reference, January 2001Synchronization Uncertainty For high speed mixed-signal applications, the key is to

Synchronization 7 Analog ModulesSystem Reference, January 2001255The following describes the details of how to remove the synchronization uncertainty

7 Analog Modules Synchronization256 System Reference, January 2001Figure 120 Trigger Signal Edge Placement when TRGL Is Set to Trigger Line Length m•

Synchronization 7 Analog ModulesSystem Reference, January 2001257Figure 121 Trigger Signal Edge Placement when TRGL Is Set to ZeroIn addition, to comp

7 Analog Modules Synchronization258 System Reference, January 2001The following timing chart is for when the value of TRGL is set to the trigger line

Synchronization 7 Analog ModulesSystem Reference, January 2001259The following timing chart is for when the TRGL value is set to zero. Figure 123 Trig

1 System Overview Major Components26 System Reference, January 2001Cooling The testhead is water cooled. It receives its supply of cooling water from

7 Analog Modules Synchronization260 System Reference, January 2001Master Trigger FunctionWhen performing tests using multiple channels of high speed a

Synchronization 7 Analog ModulesSystem Reference, January 2001261Figure124 “Master-Slave” Internal ConnectionsYou can define any module in the loop of

7 Analog Modules Synchronization262 System Reference, January 2001Figure 125 Examples of Definition of Master/Slave ModulesOne master module can suppo

Synchronization 7 Analog ModulesSystem Reference, January 2001263control the trigger-to-signal delay for the master and slaves to the same time. Hence

7 Analog Modules Synchronization264 System Reference, January 2001

Test Setup, January 2001 265Appendices

266 Test Setup, January 2001

System Reference, January 2001 267AA XICOR EEPROM SummaryOn the next page you find the XICOR X24C04 EEPROM summary supplied by XICOR. This same summar

REV 1.1 7/12/00 Characteristics subject to change without notice. 1 of 13 www.xicor.com Recommended System Management Alternative: X4043 NOT REC

X24C04 Characteristics subject to change without notice. 2 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS PIN DESCRIPTIONSSer

Major Components 1 System OverviewSystem Reference, January 200127The Support RackThe support rack is attached to the manipulator. The support rack is

X24C04 Characteristics subject to change without notice. 3 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS Stop Condition All

X24C04 Characteristics subject to change without notice. 4 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS Figure 3. Acknowled

X24C04 Characteristics subject to change without notice. 5 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS Figure 5. Byte Writ

X24C04 Characteristics subject to change without notice. 6 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS Flow 1. ACK Polling

X24C04 Characteristics subject to change without notice. 7 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS Figure 8. Random Re

X24C04 Characteristics subject to change without notice. 8 of 13REV 1.1 7/12/00 www.xicor.com NOT RECOMMENDEDFOR NEW DESIGNS ABSOLUTE MAXIMUM RA

X24C04Characteristics subject to change without notice. 9 of 13REV 1.1 7/12/00www.xicor.comNOT RECOMMENDEDFOR NEW DESIGNSA.C. CONDITIONS OF TEST E

X24C04Characteristics subject to change without notice. 10 of 13REV 1.1 7/12/00www.xicor.comNOT RECOMMENDEDFOR NEW DESIGNSBus TimingWrite Cycle Li

X24C04Characteristics subject to change without notice. 11 of 13REV 1.1 7/12/00www.xicor.comNOT RECOMMENDEDFOR NEW DESIGNSGuidelines for Calculati

X24C04Characteristics subject to change without notice. 12 of 13REV 1.1 7/12/00www.xicor.comNOT RECOMMENDEDFOR NEW DESIGNSPACKAGING INFORMATION0.1

1 System Overview Major Components28 System Reference, January 2001Primary Power Box The primary power box inside the support rack contains the connec

NOT RECOMMENDEDFOR NEW DESIGNSX24C04Characteristics subject to change without notice. 13 of 13LIMITED WARRANTYDevices sold by Xicor, Inc. are cove

IndexSystem Reference, January 2001269Index#128 pins modules 3850 Ohm impedance 118AAC/DC Converters 28Active load 122Adjusting synchronization timing

Index270 System Reference, January 2001FF330 style DUT board 63filling algorithmanalog dominant configuration1024 pin test head 77512 pin test head 75

IndexSystem Reference, January 2001271MManipulator 26Master clock 49Available sources 55Distribution 51Master Clock Generator 43Master trigger functio

Index272 System Reference, January 2001Voltage clamp 122Voltage measurement 178WWarning lamps 33Waveform Digitizer 203Functions 203Specifications 203W

Major Components 1 System OverviewSystem Reference, January 200129In order to adapt to various environments, Agilent Tech-nologies offers two differen

System Reference, January 2001 3PrefaceObjectives of this ManualThe manual provides information about the properties of the specific test system hardw

1 System Overview Major Components30 System Reference, January 2001During test program execution, upload and download are typically not necessary, sin

System Reference, January 2001 3122 System StartupThis chapter provides you with information on:• “Switching the Tester On” on page 32• “Running the S

2 System Startup Switching the Tester On32 System Reference, January 2001Switching the Tester OnThe ON/OFF Unit is integrated in the front panel of th

Switching the Tester On 2 System StartupSystem Reference, January 200133Figure 13 ON ButtonGreen flashing (slow): The system starts cooling and connec

2 System Startup Running the System Software34 System Reference, January 2001Running the System SoftwareTo start the SmarTest software, at the HP work

Switching the Tester Off 2 System StartupSystem Reference, January 200135Switching the Tester OffTo switch off the Agilent 93000 SOC Series test syste

2 System Startup Switching the Tester Off36 System Reference, January 2001Emergency OffIn case of emergency:Press the red Emergency OFF button on the

System Reference, January 2001 3733 Hardware ComponentsThis chapter provides you with information on:• “Tester Electronics” on page 38• “Parametric Me

3 Hardware Components Tester Electronics38 System Reference, January 2001Tester ElectronicsThe complete tester electronics for up to 512 DUT pins (512

Tester Electronics 3 Hardware ComponentsSystem Reference, January 200139Figure 16 Tester Electronics Inside a 512 Pins Testhead128 pinsmodu le

Preface4 System Reference, January 2001Safety InformationThe following general safety precautions must be observed during all phases of operation, ser

3 Hardware Components Tester Electronics40 System Reference, January 2001Components Inside a 128 Pins ModuleDevice Power Supply The device power suppl

Tester Electronics 3 Hardware ComponentsSystem Reference, January 200141Channel Boards 4 resp. 8 channels are grouped on one channel module. Each test

3 Hardware Components Tester Electronics42 System Reference, January 2001The figure below depicts the pin electronics on a channel board.Figure 19 Cha

Tester Electronics 3 Hardware ComponentsSystem Reference, January 200143Clock Board The Clock Board provides the following resources shared by the dig

3 Hardware Components Tester Electronics44 System Reference, January 2001Analog Modules For precision mixed-signal testing, Agilent 93000 can have the

Parametric Measurement Units 3 Hardware ComponentsSystem Reference, January 200145Parametric Measurement UnitsThe SOC Series is equipped with two type

3 Hardware Components Parametric Measurement Units46 System Reference, January 2001The figure below shows the settling time of the parallel Pin PMU me

Parametric Measurement Units 3 Hardware ComponentsSystem Reference, January 200147High-Precision PMUFor high-precision value measurements, the SOC Ser

3 Hardware Components Parametric Measurement Units48 System Reference, January 2001Table 2 HPPMU Connections, SOC 512 DUT I/FTable 3 HPPMU Connections

Master Clock System 3 Hardware ComponentsSystem Reference, January 200149Master Clock SystemThe master clock is the timing reference for all timings,

Table of ContentsSystem Reference, January 20015Table of ContentsPreface 3Objectives of this Manual 3Audience 3Scope of the Manual 3Safety Information

3 Hardware Components Master Clock System50 System Reference, January 2001In each clock domain, you can select a master clock source from the internal

Master Clock System 3 Hardware ComponentsSystem Reference, January 200151For the master clock generator on the clock board,Note that there are some re

3 Hardware Components Master Clock System52 System Reference, January 2001All master clock sources are phase-locked on the distrib-uted 10 MHz referen

Master Clock System 3 Hardware ComponentsSystem Reference, January 200153Figure25 Master Clock Distribution on 512-Pin TestheadClock BoardDigital Boar

3 Hardware Components Master Clock System54 System Reference, January 2001Figure 26 Master Clock Distribution on 1024-Pin TestheadClock BoardDigital B

Master Clock System 3 Hardware ComponentsSystem Reference, January 200155Available Master ClockSourcesAvailable master clock sources for tester hardwa

3 Hardware Components Master Clock System56 System Reference, January 2001

System Reference, January 2001 5744 Test Head Filling and DUT Board ConsiderationsThis chapter covers the DUT board structure and how to equip the tes

4 Test Head Filling and DUT Board Considerations58 System Reference, January 2001Web Address of the DUT BoardDesign GuideTogether with the Drawings a

Overview of Test Heads 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200159Overview of Test HeadsThe Agilent 93000 SOC Ser

Table of Contents6 System Reference, January 2001The Workstation 292 System Startup 31Switching the Tester On 32Switching Procedure 32Warning Lamps 33

4 Test Head Filling and DUT Board Considerations Overview of Test Heads60 System Reference, January 2001Structure of Card CagesFigure 28 illustrates t

DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200161DUT Board Mechanical Consideration

4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations62 System Reference, January 2001Instead of •a packaged parts DUT

DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200163Figure 30 DUT board options depend

4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations64 System Reference, January 2001Allocation on the 512 pin DUT Boa

DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200165Allocation on the 1024 pin DUT Boa

4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations66 System Reference, January 2001Possible 256 pin DUT boards for e

DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200167Make sure that your 256 pin DUT bo

4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations68 System Reference, January 2001column is currently not in use fo

DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200169Figure 34 Position of Analog and D

Table of ContentsSystem Reference, January 20017DUT Board of Wafer Prober 105 Probe Card-Pogo Pad Assignment 1075 DUT Board Performance Considerations

4 Test Head Filling and DUT Board Considerations Test System Configuration70 System Reference, January 2001Test System ConfigurationThere are two type

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200171Digital Dominant ConfigurationThe first part

4 Test Head Filling and DUT Board Considerations Test System Configuration72 System Reference, January 2001There is a filling algorithm for filling th

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200173Figure36 Group reservation of the digital do

4 Test Head Filling and DUT Board Considerations Test System Configuration74 System Reference, January 2001This system configuration has a maximum ana

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200175The unshaded (white) groups in Figure 37 can

4 Test Head Filling and DUT Board Considerations Test System Configuration76 System Reference, January 20012. The reservation of groups of the analog

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200177There is a filling algorithm for filling the

4 Test Head Filling and DUT Board Considerations Test System Configuration78 System Reference, January 2001Overview of FillingThe card cage filling op

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200179single group will be supported. NOTE that on

Table of Contents8 System Reference, January 2001Current and Voltage Measurements with DPS 164High Current Power Supply (HCDPS) 168HCDPS General Descr

4 Test Head Filling and DUT Board Considerations Test System Configuration80 System Reference, January 2001List of Analog InstrumentsIn Table 5, the a

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200181Analog Fill OrderThe order of analog filling

4 Test Head Filling and DUT Board Considerations Test System Configuration82 System Reference, January 2001The fill order of the cages is marked above

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200183Table 6 Analog Instruments, Count and Fillin

4 Test Head Filling and DUT Board Considerations Test System Configuration84 System Reference, January 2001Figure 41 Fill Order of Analog Instruments

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200185optional TIAs on top ( marked “slot b” in th

4 Test Head Filling and DUT Board Considerations Test System Configuration86 System Reference, January 2001DPS-Type Fill OrderAs illustrated in Figure

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200187A DPS block each requires a DPS card in the

4 Test Head Filling and DUT Board Considerations Test System Configuration88 System Reference, January 2001Table 9 DPS-Types Sub-Sequent Filling Allgo

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200189Analog Pogo Pad LocationThe pogo pads for th

Table of ContentsSystem Reference, January 20019Adjusting Synchronization Timing 249Considering Trigger-to-Signal Delay, Trigger Line, and Signal Line

4 Test Head Filling and DUT Board Considerations Test System Configuration90 System Reference, January 2001(For deeper insight in the mode of operatio

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 2001912 The pogo pin assignment for the Digitizers

4 Test Head Filling and DUT Board Considerations Test System Configuration92 System Reference, January 2001According to drawingsD-E6980-96540-1S24D(51

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200193DPS Pogo Pad Functional AssignmentExplanatio

4 Test Head Filling and DUT Board Considerations Test System Configuration94 System Reference, January 2001GPDPS and HVDPS, FunctionalAssignment of Po

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200195There are always three power pads ganged in

4 Test Head Filling and DUT Board Considerations Test System Configuration96 System Reference, January 2001therefore there are fewer pogo pads in the

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200197Utility, EEPROM and HPMUAccording to drawing

4 Test Head Filling and DUT Board Considerations Test System Configuration98 System Reference, January 2001• DSC states when the DUT board is Disconne

Test System Configuration 4 Test Head Filling and DUT Board ConsiderationsSystem Reference, January 200199Table 17 Function of Utility Pogo Pads (512